This invention relates to a semiconductor memory device, and more particularly to a dynamic metal oxide semiconductor (abbreviated as MOS) memory device.
Hitherto, a dynamic MOS memory has been widely accepted as a random access memory (abbreviated as RAM) from the standpoint of ensuring high density of integration and low power consumption. A 1-bit memory cell of the initially developed dynamic MOS memory is formed of three MOS field effect transistors (abbreviated as FETs). Where a voltage is impressed on a write word line connected to the memory cell by means of a driver provided in the memory, then data of a write bit line is written in a capacitor. Where a voltage is impressed on a read word line connected to the memory cell, then the occurrence or absence of a discharge in a read bit line, namely, a drop in the potential of the read bit line or the sustenance of the potential is denoted by the corresponding binary code of "0" or "1."
With the above-mentioned prior art dynamic MOS memory in which each memory cell comprises three transistors, a large number of wires have to be used, presenting difficulties in appreciably increasing integration density.
For elevation of integration density, a different type of dynamic MOS memory has been proposed in which each memory cell is formed of one MOS FET and one capacitor. With this proposed memory device, the MOS FET has the drain electrode connected to a bit line, the gate electrode connected to a read-write word line, and the source electrode grounded through the capacitor. Since the MOS FET does not have an amplifying function, a signal fetched from the capacitor to the bit line has such a voltage as is arrived at by dividing a capacitor voltage by a sum of a capacitor capacitance and bit line capacitance and multiplying the resultant quotient by the capacitor capacitance. In other words, the larger the number of memory cells connected to a data line, and the larger the capacitance of the data line, then the lower the voltage level of a signal fetched from the data line. The bit line generally has a capacitance 10 to 20 times larger than that of the capacitor. Therefore, a signal fetched from the memory cell has a far lower voltage than in the case of the aforesaid memory device of the 3 transistors--1 memory cell type. Consequently, it has been demanded to provide a sense amplifier capable of effectively detecting a signal, however low its voltage level may be. However, this requirement naturally increases the cost of a memory device. Further, a pair of load transistors for driving a flip-flop type sense amplifier often have different threshold voltages, giving rise to variations of properties peculiar to such sense amplifier. These variations lead to noise whose effect cannot be overlooked. Where memory cells and a sense amplifier are extremely reduced in size for high integration, then a read signal, that is, an input signal to the sense amplifier is also considerably decreased in voltage. However, a noise occurring in the sense amplifier remains little changed in voltage. In high integration, therefore, a read signal and a noise often have substantially the same level of voltage, obstructing the regular operation of a memory device.